Topology for Distributed Energy Resources
1.Leo prabu.S 2.Vickraman.D
Abstract—In the micro grid system, the distributed energy resource (DER)-based single-phase inverter is usually adopted. In order to reduce conversion losses, the key is to save costs and size by removing any kind of transformer as well as reducing the power devices. The objective of this letter is to study a novel five-level multistring inverter topology for DERs-based dc/ac conversion system. In this study, a high step-up converter is introduced as a front-end stage to improve the conversion efficiency of conventional boost converters and to stabilize the output dc voltage of various DERs such as photovoltaic and fuel cell modules for use with the simplified multilevel inverter. The simplified multilevel inverter requires only six active switches instead of the eight required in the conventional cascaded H-bridge multilevel inverter. In addition, two active switches are operated at the line frequency. The studied multistring inverter topology offers strong advantages such as improved output waveforms, smaller filter size, and lower electromagnetic interference and total harmonics distortion. Simulation and experimental results show the effectiveness of the proposed solution.
Index Terms—DC/AC power conversion, multilevel inverter.
Introduction
IN LIGHT of public concern about global warming and climate change, much effort has been focused on the development of environmentally friendly distributed energy resources (DERs). For delivering premium electric power in terms of high efficiency, reliability, and power quality, integrating interface converters of DERs such as photovoltaic (PV), wind power, micro turbines, and fuel cells into the micro grid system has become a critical issue in recent years [1]–[4]. In such systems, most DERs usually supply a dc voltage that varies in a wide range according to various load conditions. Thus, a dc/ac power processing interface is required and is compliable with residential, industrial, and utility grid standards [4]–[7].
Leo prabu.s is with the student of final year in Department of Electrical and Electronics Engineering,C.K college of engineering and technology,cuddalore(e-mail: leoprabueee@gmail.com).
Vickraman.D is with the student of final year in Department of Electrical and Electronics Engineering,C.K college of engineering and technology,cuddalore(e-mail: vickraman.tvr@gmail.com).
Color versions of one or more of the figures in this paper are available online at http://www.leoprabueee.blogspot.com and http://www.vickraman.tvr.blogspot.com
Various converter topologies have been developed for DERs[7]–[16] that demonstrate effective power flow control performance whether in grid-connected or stand-alone operation. Among them, solutions that employ high-frequency transformers or make no use of transformers at all have been investigated to reduce size, weight, and expense. For low-medium power applications, international standards allow the use of grid-connected power converters without galvanic isolation, thus allowing so called “transformerless” architectures [7], [11], [12]. Furthermore, as the output voltage level increases, the output harmonic content of such inverters decreases, allowing the use of smaller and less expensive output filters.
As a result, various multilevel topologies are usually characterized by a strong reduction in switching voltages across power switches, allowing the reduction of switching power losses and electromagnetic interference (EMI) [8], [11], [12]. A single-phase multistring five-level inverter integrated with an auxiliary circuit was recently proposed for dc/ac power conversion [12], [13]. This topology used in the power stage offers an important improvement in terms of lower component count and reduced output harmonics. Unfortunately, high switching losses in the additional auxiliary circuit caused the efficiency of the multistring five-level inverter to be approximately 4% less than that of the conventional multistring three-level inverter [13]. In [14], a novel isolated single-phase inverter with generalized zero vectors (GZV) modulation scheme was first presented to simplify the configuration. However, this circuit can still only operate in a limited voltage range for practical applications and suffer degradation in the overall efficiency as the duty cycle of the dc-side switch of the front-end conventional boost converter approaches unity [6], [14]. Furthermore, the use of isolated transformer with multi windings of the GZV based inverter results in the larger size, weight, and additional expense [14].
To overcome the aforementioned problem, the objective of this letter is to study a newly constructed transformerless five level multistring inverter topology for DERs. In this letter, the aforesaid GZV-based inverter is reduced to a multistring multilevel inverter topology that requires only six active switches instead of the eight required in the conventional cascaded H bridge (CCHB) multilevel inverter [16]. In addition, among them, two active switches are operated at the line frequency.
In order to improve the conversion efficiency of conventional boost converters, a high step-up converter is also introduced as a front-end stage to stabilize the output dc voltage of each DER modules for use with the simplified multilevel inverter. The newly constructed inverter topology offer strong advantages such as improved output waveforms, smaller filter size, and lower EMI and total harmonics distortion (THD). In this letter, the operating principle of the developed system is described, and a prototype is constructed for verifying the effectiveness of the topology.
Configuration of multistring inverter for various DERs application.
II. SYSTEM CONFIGURATION OF OPERATION PRINCIPLES
A general overview of different types of PV modules or fuel cell inverters is given in [9] and [11]. This letter presents a multistring multilevel inverter for DERs application. The multistring inverter shown in Fig. 1 is a further development of the string inverter, whereby several strings are interfaced with their own dc/dc converter to a common inverter [15]. This centralized system is beneficial because each string can be controlled individually. Thus, the operator may start his own PV/fuel cell power plant with a few modules. Further enlargements are easily achieved because a new string with a dc/dc converter can be plugged into the existing platform, enabling a flexible design with high efficiency [9]. The single-phase multistring multilevel inverter topology used in this study is shown.
This topology configuration consists of two high step-up dc/dc converters connected to their individual dc-bus capacitor and a simplified multilevel inverter. Input sources, DER module 1, and DER module 2 are connected to the inverter followed a linear resistive load through the high step-up dc/dc converters. The studied simplified five-level inverter is used instead of a conventional cascaded pulse width-modulated (PWM) inverter because it offers strong advantages such as improved output waveforms, smaller filter size, and lower EMI and THD [14]. It should be noted that, by using the independent voltage regulation control of the individual high step-up converter, voltage balance control for the two bus capacitors Cbus1, Cbus2 can be achieved naturally.
A. High Step-Up Converter Stage
In this study, high step-up converter topology is introduced to boost and stabilize the output dc voltage of various DERs such as PV and fuel cell modules for employment of the proposed simplified multilevel inverter. The architecture of a high step-up converter initially introduces and is composed of different converter topologies:
Boost, fly back, and a charge-pump circuit.
The coupled inductor of the high step-up converter can be modeled as an ideal transformer, a magnetizing inductor, and a leakage inductor. According to the voltage–seconds balance condition of the magnetizing inductor, the voltage of the primary winding can be derived as
Vpri = Vin ・ D/1 – D
Where, Vin represents each the low-voltage dc energy input sources.
B. Simplified Multilevel Inverter Stage
To assist in solving problems caused by cumbersome power stages and complex control circuits for conventional multilevel inverters, this letter reports a new single-phase multistring topology, presented as a new basic circuitry, it should be assumed that, in this configuration, the two capacitors in the capacitive voltage divider are connected directly across the dc bus, and all switching combinations are activated in an output cycle. The dynamic voltage balance between the two capacitors is automatically controlled by the preceding high step-up converter stage.
Then, we can assume Vs1 = Vs2 = Vs.
This topology includes six power switches—two fewer than the CCHB inverter with eight power switches—which drastically reduces the power circuit complexity and simplifies modulator circuit design and implementation. The phase disposition (PD) PWM control scheme is introduced to generate switching signals and to produce five output-voltage levels: 0, VS, 2VS, −VS, and −2VS.
Single-phase multistring five-level inverter topology.
Table 1
Table I lists switching combinations that generate the required five output levels. The corresponding operation modes of the multilevel inverter stage are described clearly as follows.
1) Maximum positive output, 2VS: Active switches Sa 2, Sb1, and Sb3 are ON; the voltage applied to the LC output filter is 2VS.
2) Half-level positive output, +Vs.: This output condition can be induced by two different switching combinations. One switching combination is such that active switches Sa 2, Sb1, and Sa 3 are ON; the other is such that active switches Sa 2, Sa1, and Sb3 are ON. During this operating stage, the voltage applied to the LC output filter is +Vs.
4) Half-level negative output −Vs: This output condition can be induced by either of the two different switching combinations. One switching combination is such that active switches Sa1, Sb2, and Sb3 are ON; the other is such that active switches Sa 3, Sb1, and Sb2 are ON.
5) Maximum negative output −2Vs: During this stage, active switches Sa 1, Sa 3, and Sb2 are ON, and the voltage applied to the LC output filter is −2Vs.
In these operations, it can be observed that the open voltage stress of the active power switches Sa 1 , Sa 3 , Sb 1 , and Sb 3 is equal to input voltage VS ; moreover, the main active switches Sa 2 and Sb 2 are operated at the line frequency. Hence, the resulting switching losses of the new topology are reduced naturally, and the overall conversion efficiency is improved. To verify the feasibility of the single-phase five-level inverter, a widely used software program PSIM is applied to simulate the circuit according to the previously mentioned operation principle.
The simulated waveform of the phase voltage with five levels is shown. The switch voltages of Sa1, Sa2, Sa3, Sb1, Sb2, and Sb3 are all shown. It is evident that the voltage stresses of the switches Sa1, Sa3, Sb1, and Sb3 are all equal to 100V, and only the other two switches Sa2, Sb2 must be 200V voltage stress.
III. EXPERIMENTAL RESULTS
To facilitate understanding of the operating principle and as verification, a prototype system with a high step-up dc/dc converter stage and the simplified multilevel dc/ac stage are built with the corresponding parameters listed in Table V.
The specifications of the two preceding high step-up dc/dc converters are 1) input voltage 30V; 2) controlled output voltage 100V; and 3) switching frequency 85 kHz. The corresponding specifications of the simplified multilevel dc/ac inverter stage are 1) output power, Po = 230W; 2) input voltage, Vs = 100V; 3) output voltage, vo =110Vrms ; 4) line frequency, fm =60 Hz; 5) switching frequency, fs = 40 kHz; and 6) peak modulation index, mpeak = 0.76.
Measured waveforms of output voltage vo , output current io, and voltage applied to LC filter terminal VAB .
For better understanding, the guidelines and considerations of the dc-link capacitance and the use of an LC output filter at the output are described as follows.
- Sizing DC-link Capacitor
For the discussed two-stage dc/ac conversion system, the dc link capacitance is sized to keep voltage fluctuations within specified limits to prevent over-voltage on the dc bus. To calculate the relationship between capacitance and voltage limits, the net power flowing into the bus capacitor.
For the discussed two-stage conversion system in this study, a design limit of maximum ΔVbus = 10V is chosen to keep the bus voltage well within the voltage rating of the semiconductors, which now is typically 200V, and to minimize the third-order harmonic occurring on the output voltage. For the aforementioned considerations, the capacitanceCbus1 and Cbus1 are now chosen as 2000 μF, respectively. It should be noted that, for simplification, the bus capacitance for this case is only selected based on voltage deviation specifications.
B. Choice of Output LC Filter
The output LC filter is tuned to below the switching frequency as follows:
√LoCo ≥ 1/2πfs
Where fs is the switching frequency, and Lo and Co are inductance and capacitance of the output LC filter, respectively.
The experimental results of the simplified single-phase inverter stage operated at the rated output power are shown. It is evident that the voltage stresses of the switches Sa1 , Sa3 , Sb1 , and Sb3 are all equal to 100V, and only the other two switches Sa2 , Sb2 must be 200V voltage stress. Fig. 10 shows steady state waveforms of output voltage vo , output current io, and the voltage applied to LC output filter terminal VAB, respectively, for the inverter with a resistive load of 51 ΩAs can be seen in Fig. 10, the waveform shows the desired five voltage levels: 200, 100, 0, −100, and −200V. The measured rms value of VO is approximately 110V, while the measured rms value of io is approximately 2.12 A. The conversion efficiency of the implemented inverter and THD of the output voltage measured in this case are approximately 96% and 3%, respectively.
IV. CONCLUSION
This letter reports a single-phase multistring multilevel inverter topology that produces a significant reduction in the number of power devices required to implement multilevel output for DERs. The studied inverter topology offer strong advantages such as improved output waveforms, smaller filter size, and lower EMI and THD. Simulation and experimental results show the effectiveness of the proposed solution.
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